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authorKevin Laeufer2021-02-17 12:16:52 -0800
committerGitHub2021-02-17 20:16:52 +0000
commit5a89fca6090948d0a99c217a09c692e58a20d1df (patch)
tree7996829e3589205607862cbbf578a4e9a9d6e623 /src/main/scala/firrtl/ir/Serializer.scala
parent856226416cfa2d770c7205efad5331297c2e3a32 (diff)
Allow Side Effecting Statement to have Names (#2057)
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
Diffstat (limited to 'src/main/scala/firrtl/ir/Serializer.scala')
-rw-r--r--src/main/scala/firrtl/ir/Serializer.scala18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/ir/Serializer.scala b/src/main/scala/firrtl/ir/Serializer.scala
index 983a7866..caea0a9c 100644
--- a/src/main/scala/firrtl/ir/Serializer.scala
+++ b/src/main/scala/firrtl/ir/Serializer.scala
@@ -102,11 +102,13 @@ object Serializer {
s(it.next())
if (it.hasNext) newLineAndIndent()
}
- case Stop(info, ret, clk, en) =>
- b ++= "stop("; s(clk); b ++= ", "; s(en); b ++= ", "; b ++= ret.toString; b += ')'; s(info)
- case Print(info, string, args, clk, en) =>
+ case stop @ Stop(info, ret, clk, en) =>
+ b ++= "stop("; s(clk); b ++= ", "; s(en); b ++= ", "; b ++= ret.toString; b += ')'
+ sStmtName(stop.name); s(info)
+ case print @ Print(info, string, args, clk, en) =>
b ++= "printf("; s(clk); b ++= ", "; s(en); b ++= ", "; b ++= string.escape
- if (args.nonEmpty) b ++= ", "; s(args, ", "); b += ')'; s(info)
+ if (args.nonEmpty) b ++= ", "; s(args, ", "); b += ')'
+ sStmtName(print.name); s(info)
case IsInvalid(info, expr) => s(expr); b ++= " is invalid"; s(info)
case DefWire(info, name, tpe) => b ++= "wire "; b ++= name; b ++= " : "; s(tpe); s(info)
case DefRegister(info, name, tpe, clock, reset, init) =>
@@ -138,9 +140,9 @@ object Serializer {
case Attach(info, exprs) =>
// exprs should never be empty since the attach statement takes *at least* two signals according to the spec
b ++= "attach ("; s(exprs, ", "); b += ')'; s(info)
- case Verification(op, info, clk, pred, en, msg) =>
+ case veri @ Verification(op, info, clk, pred, en, msg) =>
b ++= op.toString; b += '('; s(List(clk, pred, en), ", ", false); b ++= msg.escape
- b += ')'; s(info)
+ b += ')'; sStmtName(veri.name); s(info)
// WIR
case firrtl.CDefMemory(info, name, tpe, size, seq, readUnderWrite) =>
@@ -155,6 +157,10 @@ object Serializer {
case other => b ++= other.serialize // Handle user-defined nodes
}
+ private def sStmtName(lbl: String)(implicit b: StringBuilder): Unit = {
+ if (lbl.nonEmpty) { b ++= s" : $lbl" }
+ }
+
private def s(node: Width)(implicit b: StringBuilder, indent: Int): Unit = node match {
case IntWidth(width) => b += '<'; b ++= width.toString(); b += '>'
case UnknownWidth => // empty string