diff options
| author | Schuyler Eldridge | 2019-12-17 18:29:47 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-03-11 14:01:31 -0400 |
| commit | abf226471249a1cbb8de33d0c4bc8526f9aafa70 (patch) | |
| tree | 0537dff3091db3da167c0fffc3388a5966c46204 /src/main/scala/firrtl/checks | |
| parent | 646c91e71b8bfb1b0d0f22e81ca113147637ce71 (diff) | |
Migrate to DependencyAPI
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/checks')
| -rw-r--r-- | src/main/scala/firrtl/checks/CheckResets.scala | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/checks/CheckResets.scala b/src/main/scala/firrtl/checks/CheckResets.scala index d6337f9e..406b7f62 100644 --- a/src/main/scala/firrtl/checks/CheckResets.scala +++ b/src/main/scala/firrtl/checks/CheckResets.scala @@ -3,6 +3,7 @@ package firrtl.checks import firrtl._ +import firrtl.options.{Dependency, PreservesAll} import firrtl.passes.{Errors, PassException} import firrtl.ir._ import firrtl.traversals.Foreachers._ @@ -25,10 +26,19 @@ object CheckResets { // Must run after ExpandWhens // Requires // - static single connections of ground types -class CheckResets extends Transform { +class CheckResets extends Transform with PreservesAll[Transform] { def inputForm: CircuitForm = MidForm def outputForm: CircuitForm = MidForm + override val prerequisites = + Seq( Dependency(passes.LowerTypes), + Dependency(passes.Legalize), + Dependency(firrtl.transforms.RemoveReset) ) ++ firrtl.stage.Forms.MidForm + + override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.CheckCombLoops]) + + override val dependents = Seq.empty + import CheckResets._ private def onStmt(regCheck: RegCheckList, drivers: DirectDriverMap)(stmt: Statement): Unit = { @@ -72,4 +82,3 @@ class CheckResets extends Transform { state } } - |
