diff options
| author | Aditya Naik | 2024-05-29 16:57:13 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-05-29 16:57:13 -0700 |
| commit | 165804ee58cb18443042b9655328278434ddedf4 (patch) | |
| tree | 4e167eff9e7b3ec09d73dbd9feaa6f9964cd8a68 /src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | |
| parent | 57b8a395ee8d5fdabb2deed3db7d0c644f0a7eed (diff) | |
Add Scala3 support
Diffstat (limited to 'src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala index 30d2e891..2634a8e1 100644 --- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala +++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala @@ -511,7 +511,7 @@ class VerilogEmitter extends SeqTransform with Emitter { } private val emissionAnnos = annotations.collect { - case m: SingleTargetAnnotation[ReferenceTarget] @unchecked with EmissionOption => m + case m: SingleTargetAnnotation[ReferenceTarget] @unchecked & EmissionOption => m } annotations.foreach { |