Refactor emiter (#1879)

* split big Emitter to submodules.

* fix all deprecated warning.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 31 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/backends/verilog/SystemVerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/SystemVerilogEmitter.scala
new file mode 100644
index 00000000..2d8e3089
--- /dev/null
+++ b/src/main/scala/firrtl/backends/verilog/SystemVerilogEmitter.scala
@@ -0,0 +1,31 @@
+package firrtl
+
+import firrtl.ir.{Expression, Info, StringLit}
+
+import scala.collection.mutable
+import scala.collection.mutable.ArrayBuffer
+
+class SystemVerilogEmitter extends VerilogEmitter {
+  override val outputSuffix: String = ".sv"
+
+  override def prerequisites = firrtl.stage.Forms.LowFormOptimized
+
+  override def addFormalStatement(
+    formals: mutable.Map[Expression, ArrayBuffer[Seq[Any]]],
+    clk:     Expression,
+    en:      Expression,
+    stmt:    Seq[Any],
+    info:    Info,
+    msg:     StringLit
+  ): Unit = {
+    val lines = formals.getOrElseUpdate(clk, ArrayBuffer[Seq[Any]]())
+    lines += Seq("// ", msg.serialize)
+    lines += Seq("if (", en, ") begin")
+    lines += Seq(tab, stmt, info)
+    lines += Seq("end")
+  }
+
+  override def execute(state: CircuitState): CircuitState = {
+    super.execute(state)
+  }
+}