Remove some warnings (#2448)

* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth

1 files changed, 2 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala b/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
index a5f7f81f..6c6c0b69 100644
--- a/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
+++ b/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
@@ -880,6 +880,8 @@ private[firrtl] class RtlilEmitter extends SeqTransform with Emitter with Depend
               println("Leaving memory uninitialized.")
             case MemoryFileInlineInit(_, _) =>
               throw EmitterException(s"Memory $name cannot be initialized from a file, RTLIL cannot express this.")
+            case MemoryNoInit =>
+            // No initialization to emit
           }
           for (r <- rd) {
             val data = memPortField(x, r, "data")