Merge pull request #1852 from freechipsproject/format-src-4

Apply Scalafmt Rewriting

1 files changed, 5 insertions, 7 deletions

diff --git a/src/main/scala/firrtl/annotations/PresetAnnotations.scala b/src/main/scala/firrtl/annotations/PresetAnnotations.scala
index 727417c1..d6066aa7 100644
--- a/src/main/scala/firrtl/annotations/PresetAnnotations.scala
+++ b/src/main/scala/firrtl/annotations/PresetAnnotations.scala
@@ -10,11 +10,11 @@ package annotations
   * @param target ReferenceTarget to an AsyncReset
   */
 case class PresetAnnotation(target: ReferenceTarget)
-    extends SingleTargetAnnotation[ReferenceTarget] with firrtl.transforms.DontTouchAllTargets {
+    extends SingleTargetAnnotation[ReferenceTarget]
+    with firrtl.transforms.DontTouchAllTargets {
   override def duplicate(n: ReferenceTarget) = this.copy(target = n)
 }
 
-
 /**
   * Transform the targeted asynchronously-reset Reg into a bitstream preset Reg
   * Used internally to annotate all registers associated to an AsyncReset tree
@@ -22,12 +22,10 @@ case class PresetAnnotation(target: ReferenceTarget)
   * @param target ReferenceTarget to a Reg
   */
 private[firrtl] case class PresetRegAnnotation(
-  target: ReferenceTarget
-) extends SingleTargetAnnotation[ReferenceTarget] with RegisterEmissionOption {
+  target: ReferenceTarget)
+    extends SingleTargetAnnotation[ReferenceTarget]
+    with RegisterEmissionOption {
   def duplicate(n: ReferenceTarget) = this.copy(target = n)
   override def useInitAsPreset = true
   override def disableRandomization = true
 }
-
-
-