diff options
| author | Jack Koenig | 2020-08-15 10:16:28 -0700 |
|---|---|---|
| committer | GitHub | 2020-08-15 10:16:28 -0700 |
| commit | f1c314e6c7e116df33ffc215ec907212037292dc (patch) | |
| tree | f06060e9fb52f4f5b30bc56db78acb6bd371642d /src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala | |
| parent | 2e5f942d25d7afab79ee1263c5d6833cad9d743d (diff) | |
| parent | 9adbe1ede59f9aeb25e71fd8318a4e7e46c4cc34 (diff) | |
Merge pull request #1852 from freechipsproject/format-src-4
Apply Scalafmt Rewriting
Diffstat (limited to 'src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala')
| -rw-r--r-- | src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala b/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala index 44a8e3b5..7cefdef8 100644 --- a/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala +++ b/src/main/scala/firrtl/annotations/MemoryInitAnnotation.scala @@ -5,10 +5,10 @@ package firrtl.annotations import firrtl.{MemoryArrayInit, MemoryEmissionOption, MemoryInitValue, MemoryRandomInit, MemoryScalarInit} /** - * Represents the initial value of the annotated memory. - * While not supported on normal ASIC flows, it can be useful for simulation and FPGA flows. - * This annotation is consumed by the verilog emitter. - */ + * Represents the initial value of the annotated memory. + * While not supported on normal ASIC flows, it can be useful for simulation and FPGA flows. + * This annotation is consumed by the verilog emitter. + */ sealed trait MemoryInitAnnotation extends SingleTargetAnnotation[ReferenceTarget] with MemoryEmissionOption { def isRandomInit: Boolean } @@ -16,20 +16,20 @@ sealed trait MemoryInitAnnotation extends SingleTargetAnnotation[ReferenceTarget /** Randomly initialize the `target` memory. This is the same as the default behavior. */ case class MemoryRandomInitAnnotation(target: ReferenceTarget) extends MemoryInitAnnotation { override def duplicate(n: ReferenceTarget): Annotation = copy(n) - override def initValue: MemoryInitValue = MemoryRandomInit + override def initValue: MemoryInitValue = MemoryRandomInit override def isRandomInit: Boolean = true } /** Initialize all entries of the `target` memory with the scalar `value`. */ case class MemoryScalarInitAnnotation(target: ReferenceTarget, value: BigInt) extends MemoryInitAnnotation { override def duplicate(n: ReferenceTarget): Annotation = copy(n) - override def initValue: MemoryInitValue = MemoryScalarInit(value) - override def isRandomInit: Boolean = false + override def initValue: MemoryInitValue = MemoryScalarInit(value) + override def isRandomInit: Boolean = false } /** Initialize the `target` memory with the array of `values` which must be the same size as the memory depth. */ case class MemoryArrayInitAnnotation(target: ReferenceTarget, values: Seq[BigInt]) extends MemoryInitAnnotation { override def duplicate(n: ReferenceTarget): Annotation = copy(n) - override def initValue: MemoryInitValue = MemoryArrayInit(values) - override def isRandomInit: Boolean = false -}
\ No newline at end of file + override def initValue: MemoryInitValue = MemoryArrayInit(values) + override def isRandomInit: Boolean = false +} |
