Merge pull request #1852 from freechipsproject/format-src-4

Apply Scalafmt Rewriting

1 files changed, 4 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/analyses/CircuitGraph.scala b/src/main/scala/firrtl/analyses/CircuitGraph.scala
index 506bba57..a1fb0f19 100644
--- a/src/main/scala/firrtl/analyses/CircuitGraph.scala
+++ b/src/main/scala/firrtl/analyses/CircuitGraph.scala
@@ -80,9 +80,10 @@ class CircuitGraph private[analyses] (connectionGraph: ConnectionGraph) {
     * @return
     */
   def absolutePaths(mt: ModuleTarget): Seq[IsModule] = instanceGraph.findInstancesInHierarchy(mt.module).map {
-    case seq if seq.nonEmpty => seq.foldLeft(CircuitTarget(circuit.main).module(circuit.main): IsModule) {
-      case (it, InstanceKey(instance, ofModule)) => it.instOf(instance, ofModule)
-    }
+    case seq if seq.nonEmpty =>
+      seq.foldLeft(CircuitTarget(circuit.main).module(circuit.main): IsModule) {
+        case (it, InstanceKey(instance, ofModule)) => it.instOf(instance, ofModule)
+      }
   }
 
   /** Return the sequence of nodes from source to sink, inclusive