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authorazidar2016-02-09 13:14:52 -0800
committerazidar2016-02-09 18:57:08 -0800
commit57473f4c6a9f35752bb71fc7b8d6b54471aeaa07 (patch)
tree9425ee401579fa3472cd4f2160f0a1258fee9361 /src/main/scala/firrtl/WIR.scala
parente63a058b04d428cd407528b0276cc0413b581be2 (diff)
CHIRRTL passes work, parser is updated
Diffstat (limited to 'src/main/scala/firrtl/WIR.scala')
-rw-r--r--src/main/scala/firrtl/WIR.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index eaa4166b..61657879 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -190,6 +190,6 @@ case object MRead extends MPortDir
case object MWrite extends MPortDir
case object MReadWrite extends MPortDir
-case class CDefMemory (val info: FileInfo, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Stmt
-case class CDefMPort (val info: FileInfo, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Stmt
+case class CDefMemory (val info: Info, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Stmt
+case class CDefMPort (val info: Info, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Stmt