diff options
| author | Andrew Waterman | 2019-01-23 13:27:19 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2019-01-23 13:27:19 -0800 |
| commit | 1738c1ef0ac95fae25d52586b3b0348de80de2ff (patch) | |
| tree | e28d770a8ad05b7f9635365248ee6a44a766714e /src/main/scala/firrtl/WIR.scala | |
| parent | df3c3fb5eedd3e2ac95b9f210268e4e515d6344c (diff) | |
Improve Shl codegen; eliminate Shlw WIR node (#994)
* Improve Shl codegen; eliminate Shlw WIR node
If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass. Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.
* [skip formal checks] Add test
Diffstat (limited to 'src/main/scala/firrtl/WIR.scala')
| -rw-r--r-- | src/main/scala/firrtl/WIR.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala index a5d2571d..0c5c250f 100644 --- a/src/main/scala/firrtl/WIR.scala +++ b/src/main/scala/firrtl/WIR.scala @@ -152,8 +152,6 @@ case object Addw extends PrimOp { override def toString = "addw" } case object Subw extends PrimOp { override def toString = "subw" } // Resultant width is the same as input argument width case object Dshlw extends PrimOp { override def toString = "dshlw" } -// Resultant width is the same as input argument width -case object Shlw extends PrimOp { override def toString = "shlw" } object WrappedExpression { def apply(e: Expression) = new WrappedExpression(e) |