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authorJack2016-05-09 23:33:36 -0700
committerJack Koenig2016-06-10 16:32:50 -0700
commit26e33c343332c2f65bb45bc17b40a9cb7d22e2fd (patch)
treea02cead24db710db2f1832d0e3389ad256085600 /src/main/scala/firrtl/WIR.scala
parent1eb8be78938721dd0d609f684c159bc1d1ddcfd6 (diff)
API Cleanup - Statement
trait Stmt -> abstract class Statement (to match Expression) abbrev. exp -> expr BulkConnect -> PartialConnect camelCase things that were snake_case case class Empty() -> case object EmptyStmt Change >120 character Statements to multiline
Diffstat (limited to 'src/main/scala/firrtl/WIR.scala')
-rw-r--r--src/main/scala/firrtl/WIR.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index dca1cdff..cdd00e07 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -57,7 +57,7 @@ case class WVoid() extends Expression { def tpe = UnknownType }
case class WInvalid() extends Expression { def tpe = UnknownType }
// Useful for splitting then remerging references
case object EmptyExpression extends Expression { def tpe = UnknownType }
-case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Stmt with IsDeclaration
+case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Statement with IsDeclaration
// Resultant width is the same as the maximum input width
case object ADDW_OP extends PrimOp
@@ -227,6 +227,6 @@ case object MRead extends MPortDir
case object MWrite extends MPortDir
case object MReadWrite extends MPortDir
-case class CDefMemory (val info: Info, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Stmt
-case class CDefMPort (val info: Info, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Stmt
+case class CDefMemory (val info: Info, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Statement
+case class CDefMPort (val info: Info, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Statement