diff options
| author | Jack | 2016-01-29 00:00:17 -0800 |
|---|---|---|
| committer | Jack | 2016-01-29 00:00:17 -0800 |
| commit | 676fbd9f97fcbedf351a904b645eb200c12144a5 (patch) | |
| tree | 3b89e90367e0b72ce162178839aa4add1205e53d /src/main/scala/firrtl/Visitor.scala | |
| parent | fec6fed92a116290c8944b34c3f9d720a1fa574d (diff) | |
Changed reg syntax to new "with" semantics in Scala FIRRTL
Diffstat (limited to 'src/main/scala/firrtl/Visitor.scala')
| -rw-r--r-- | src/main/scala/firrtl/Visitor.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala index a026a495..ad8d24f2 100644 --- a/src/main/scala/firrtl/Visitor.scala +++ b/src/main/scala/firrtl/Visitor.scala @@ -122,8 +122,8 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST] case "reg" => { val name = ctx.id(0).getText val tpe = visitType(ctx.`type`(0)) - val (reset, init) = if (ctx.getChildCount > 5) (visitExp(ctx.exp(1)), visitExp(ctx.exp(2))) - else (UIntValue(0, IntWidth(1)), Ref(name, tpe)) + val reset = if (ctx.exp(1) != null) visitExp(ctx.exp(1)) else UIntValue(0, IntWidth(1)) + val init = if (ctx.exp(2) != null) visitExp(ctx.exp(2)) else Ref(name, tpe) DefRegister(info, name, tpe, visitExp(ctx.exp(0)), reset, init) } case "mem" => visitMem(ctx) |