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authorJack2016-05-09 16:04:52 -0700
committerJack Koenig2016-06-10 16:31:50 -0700
commit2bf1c9e84b7affb82fd08484285250ce8f7b6f26 (patch)
tree7e2276fc5405029ec5acd75b81c985e3d61989b5 /src/main/scala/firrtl/Visitor.scala
parent83f53a3a0cdcfc7537e923b827ab820205025d45 (diff)
API Cleanup - Module
trait Module -> abstract class DefModule InModule -> Module (match concrete syntax) ExModule -> ExtModule (match concrete syntax) Add simple scaladoc for each one
Diffstat (limited to 'src/main/scala/firrtl/Visitor.scala')
-rw-r--r--src/main/scala/firrtl/Visitor.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index f2a3953b..cc6f900c 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -98,11 +98,11 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
private def visitCircuit[AST](ctx: FIRRTLParser.CircuitContext): Circuit =
Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.map(visitModule), (ctx.id.getText))
- private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module = {
+ private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): DefModule = {
val info = visitInfo(Option(ctx.info), ctx)
ctx.getChild(0).getText match {
- case "module" => InModule(info, ctx.id.getText, ctx.port.map(visitPort), visitBlock(ctx.block))
- case "extmodule" => ExModule(info, ctx.id.getText, ctx.port.map(visitPort))
+ case "module" => Module(info, ctx.id.getText, ctx.port.map(visitPort), visitBlock(ctx.block))
+ case "extmodule" => ExtModule(info, ctx.id.getText, ctx.port.map(visitPort))
}
}