diff options
| author | Jack | 2016-05-09 23:55:47 -0700 |
|---|---|---|
| committer | Jack Koenig | 2016-06-10 16:33:01 -0700 |
| commit | c1504e2179e509632fa8d9ab44d87191b46cf851 (patch) | |
| tree | 80e520a1b193590c3ae84e5b6bf81728c840ab85 /src/main/scala/firrtl/Visitor.scala | |
| parent | 26e33c343332c2f65bb45bc17b40a9cb7d22e2fd (diff) | |
API Cleanup - Expression
trait Expression -> abstract class Expression
Ref -> Reference
abbrev. exp -> expr
Add abstract class Literal
UIntValue -> UIntLiteral extends Literal
SIntValue -> SIntLiteral extends Literal
Diffstat (limited to 'src/main/scala/firrtl/Visitor.scala')
| -rw-r--r-- | src/main/scala/firrtl/Visitor.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala index cc4d9c74..db2e8b8b 100644 --- a/src/main/scala/firrtl/Visitor.scala +++ b/src/main/scala/firrtl/Visitor.scala @@ -200,8 +200,8 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST] case "reg" => { val name = (ctx.id(0).getText) val tpe = visitType(ctx.`type`(0)) - val reset = if (ctx.exp(1) != null) visitExp(ctx.exp(1)) else UIntValue(0, IntWidth(1)) - val init = if (ctx.exp(2) != null) visitExp(ctx.exp(2)) else Ref(name, tpe) + val reset = if (ctx.exp(1) != null) visitExp(ctx.exp(1)) else UIntLiteral(0, IntWidth(1)) + val init = if (ctx.exp(2) != null) visitExp(ctx.exp(2)) else Reference(name, tpe) DefRegister(info, name, tpe, visitExp(ctx.exp(0)), reset, init) } case "mem" => visitMem(ctx) @@ -251,7 +251,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST] // - Add validif private def visitExp[AST](ctx: FIRRTLParser.ExpContext): Expression = if( ctx.getChildCount == 1 ) - Ref((ctx.getText), UnknownType) + Reference((ctx.getText), UnknownType) else ctx.getChild(0).getText match { case "UInt" => { // This could be better @@ -262,7 +262,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST] val bigint = string2BigInt(ctx.IntLit(0).getText) (IntWidth(BigInt(scala.math.max(bigint.bitLength,1))),bigint) } - UIntValue(value, width) + UIntLiteral(value, width) } case "SInt" => { val (width, value) = @@ -272,7 +272,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST] val bigint = string2BigInt(ctx.IntLit(0).getText) (IntWidth(BigInt(bigint.bitLength + 1)),bigint) } - SIntValue(value, width) + SIntLiteral(value, width) } case "validif(" => ValidIf(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType) case "mux(" => Mux(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), visitExp(ctx.exp(2)), UnknownType) |