aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/Visitor.scala
diff options
context:
space:
mode:
authorJack Koenig2018-06-11 13:27:56 -0700
committerGitHub2018-06-11 13:27:56 -0700
commit535d8025412a64471d8cc9c315505a8e2cbddbe0 (patch)
tree4c52dd0a665192b55763fec2d3b47db23b561bad /src/main/scala/firrtl/Visitor.scala
parent9bd639acf58ad3a6c13b858d65845a95ddac1610 (diff)
Add utilities for UInt and SInt literals (#815)
Also minor cleanup to literal construction in Visitor
Diffstat (limited to 'src/main/scala/firrtl/Visitor.scala')
-rw-r--r--src/main/scala/firrtl/Visitor.scala45
1 files changed, 17 insertions, 28 deletions
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index c45d7f56..64249c11 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -284,9 +284,6 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
}
}
- // TODO
- // - Add mux
- // - Add validif
private def visitExp[FirrtlNode](ctx: FIRRTLParser.ExpContext): Expression = {
val ctx_exp = ctx.exp.asScala
if (ctx.getChildCount == 1)
@@ -294,32 +291,24 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
else
ctx.getChild(0).getText match {
case "UInt" =>
- // This could be better
- val (width, value) =
- if (ctx.getChildCount > 4)
- (IntWidth(string2BigInt(ctx.intLit(0).getText)), string2BigInt(ctx.intLit(1).getText))
- else {
- val bigint = string2BigInt(ctx.intLit(0).getText)
- (IntWidth(BigInt(scala.math.max(bigint.bitLength, 1))), bigint)
- }
- UIntLiteral(value, width)
+ if (ctx.getChildCount > 4) {
+ val width = IntWidth(string2BigInt(ctx.intLit(0).getText))
+ val value = string2BigInt(ctx.intLit(1).getText)
+ UIntLiteral(value, width)
+ } else {
+ val value = string2BigInt(ctx.intLit(0).getText)
+ UIntLiteral(value)
+ }
case "SInt" =>
- val (width, value) =
- if (ctx.getChildCount > 4) {
- val width = string2BigInt(ctx.intLit(0).getText)
- val value = string2BigInt(ctx.intLit(1).getText)
- (IntWidth(width), value)
- } else {
- val str = ctx.intLit(0).getText
- val value = string2BigInt(str)
- // To calculate bitwidth of negative number,
- // 1) negate number and subtract one to get the maximum positive value.
- // 2) get bitwidth of max positive number
- // 3) add one to account for the signed representation
- val width = if (value < 0) (value.abs - BigInt(1)).bitLength + 1 else value.bitLength + 1
- (IntWidth(BigInt(width)), value)
- }
- SIntLiteral(value, width)
+ if (ctx.getChildCount > 4) {
+ val width = string2BigInt(ctx.intLit(0).getText)
+ val value = string2BigInt(ctx.intLit(1).getText)
+ SIntLiteral(value, IntWidth(width))
+ } else {
+ val str = ctx.intLit(0).getText
+ val value = string2BigInt(str)
+ SIntLiteral(value)
+ }
case "validif(" => ValidIf(visitExp(ctx_exp(0)), visitExp(ctx_exp(1)), UnknownType)
case "mux(" => Mux(visitExp(ctx_exp(0)), visitExp(ctx_exp(1)), visitExp(ctx_exp(2)), UnknownType)
case _ =>