diff options
| author | Jack | 2016-02-08 23:30:57 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:07 -0800 |
| commit | d2d3260a15adaabd7b6c90587fa6bc1e8eefc4e6 (patch) | |
| tree | ffe7c06c7b0b8e1ba2388beb93a16a1c3c7c3e37 /src/main/scala/firrtl/Utils.scala | |
| parent | a9afec2145fe27a26c51fca7e169495114c5108d (diff) | |
Added migrated HighFormCheck to Scala FIRRTL, changes to IR and Utils for getting info for error reporting in new pass/check.
Diffstat (limited to 'src/main/scala/firrtl/Utils.scala')
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 339d112c..e4525560 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -905,6 +905,23 @@ object Utils { case s: DefMemory => s.data_type case _ => UnknownType() } + + def getInfo: Info = + stmt match { + case s: DefWire => s.info + case s: DefPoison => s.info + case s: DefRegister => s.info + case s: DefInstance => s.info + case s: DefMemory => s.info + case s: DefNode => s.info + case s: Conditionally => s.info + case s: BulkConnect => s.info + case s: Connect => s.info + case s: IsInvalid => s.info + case s: Stop => s.info + case s: Print => s.info + case _ => NoInfo + } } implicit class WidthUtils(w: Width) { |