Remove unnecessary $signed casts for PrimOps in Verilog Emitter

[skip formal checks]

Adds new InlineCastsTransform to the VerilogEmitter which removes
Statements that do nothing but cast by inlining the cast Expression

1 files changed, 11 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 8a76aca6..6cb309b3 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -188,6 +188,17 @@ object Utils extends LazyLogging {
     case sx => sx
   }
 
+  /** Returns true if PrimOp is a cast, false otherwise */
+  def isCast(op: PrimOp): Boolean = op match {
+    case AsUInt | AsSInt | AsClock | AsAsyncReset | AsFixedPoint => true
+    case _ => false
+  }
+  /** Returns true if Expression is a casting PrimOp, false otherwise */
+  def isCast(expr: Expression): Boolean = expr match {
+    case DoPrim(op, _,_,_) if isCast(op) => true
+    case _ => false
+  }
+
   /** Provide a nice name to create a temporary **/
   def niceName(e: Expression): String = niceName(1)(e)
   def niceName(depth: Int)(e: Expression): String = {