diff options
| author | Jack Koenig | 2019-02-14 15:08:35 -0800 |
|---|---|---|
| committer | GitHub | 2019-02-14 15:08:35 -0800 |
| commit | 2272044c6ab46b5148c39c124e66e1a8e9073a24 (patch) | |
| tree | 83ad2141b1a3c54707dd9b33073f9217b0ae16c8 /src/main/scala/firrtl/Utils.scala | |
| parent | d487b4cb6726e7e8d1a18f894021652594125221 (diff) | |
Asynchronous Reset (#1011)
Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
Diffstat (limited to 'src/main/scala/firrtl/Utils.scala')
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index f60d68b1..ae2835de 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -388,6 +388,7 @@ object Utils extends LazyLogging { def mux_type(e1: Expression, e2: Expression): Type = mux_type(e1.tpe, e2.tpe) def mux_type(t1: Type, t2: Type): Type = (t1, t2) match { case (ClockType, ClockType) => ClockType + case (AsyncResetType, AsyncResetType) => AsyncResetType case (t1: UIntType, t2: UIntType) => UIntType(UnknownWidth) case (t1: SIntType, t2: SIntType) => SIntType(UnknownWidth) case (t1: FixedType, t2: FixedType) => FixedType(UnknownWidth, UnknownWidth) @@ -406,6 +407,7 @@ object Utils extends LazyLogging { } (t1, t2) match { case (ClockType, ClockType) => ClockType + case (AsyncResetType, AsyncResetType) => AsyncResetType case (t1x: UIntType, t2x: UIntType) => UIntType(wmax(t1x.width, t2x.width)) case (t1x: SIntType, t2x: SIntType) => SIntType(wmax(t1x.width, t2x.width)) case (FixedType(w1, p1), FixedType(w2, p2)) => |