diff options
| author | Jack | 2015-10-15 13:50:36 -0700 |
|---|---|---|
| committer | Jack | 2015-10-15 13:50:36 -0700 |
| commit | 7a7936c8fbddbffc1c4775fafeb5106ba1002dd4 (patch) | |
| tree | bc3cb4d8efeb3243a63f80d2d25e9ee6282215ff /src/main/scala/firrtl/Test.scala | |
| parent | edd57efbadf493b331e69c8686662500fe859372 (diff) | |
Added infer-types pass, seems to work. Added infer-types error checking, modified Logger slightly, added Primops object for utility functions, minor changes in Utils
Diffstat (limited to 'src/main/scala/firrtl/Test.scala')
| -rw-r--r-- | src/main/scala/firrtl/Test.scala | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/Test.scala b/src/main/scala/firrtl/Test.scala index 86c3616a..3a89aeef 100644 --- a/src/main/scala/firrtl/Test.scala +++ b/src/main/scala/firrtl/Test.scala @@ -3,6 +3,7 @@ package firrtl import java.io._ import Utils._ import DebugUtils._ +import Passes._ object Test { @@ -18,22 +19,25 @@ object Test val writer = new PrintWriter(new File(output)) writer.write(ast.serialize()) writer.close() - logger.printDebug(ast) + logger.printlnDebug(ast) } private def verilog(input: String, output: String)(implicit logger: Logger) { logger.warn("Verilog compiler not fully implemented") val ast = time("parse"){ Parser.parse(input) } // Execute passes - //val ast2 = time("inferTypes"){ inferTypes(ast) } - val ast2 = ast + + logger.println("Infer Types") + val ast2 = time("inferTypes"){ inferTypes(ast) } + logger.printlnDebug(ast2) + logger.println("Finished Infer Types") + //val ast2 = ast // Output val writer = new PrintWriter(new File(output)) var outString = time("serialize"){ ast2.serialize() } writer.write(outString) writer.close() - logger.printDebug(ast2) } def main(args: Array[String]) |
