diff options
| author | Chick Markley | 2020-03-26 11:43:24 -0700 |
|---|---|---|
| committer | GitHub | 2020-03-26 18:43:24 +0000 |
| commit | 249ed127cf6bf849f9895b8b603bececba1c5d76 (patch) | |
| tree | 5313d130d40184dedf7c8b8e1608df5db2c74acd /src/main/scala/firrtl/RenameMap.scala | |
| parent | 5b58936df09163ed3f0690bd66e46b307c2a9654 (diff) | |
Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)
* Eliminate warnings on `sbt doc` and `sbt unidoc`
- removed toFirrtl reference on MultiTargetAnnotation
- lots of places where package path has to be added to comment references
- Change to use `/** text starts here` convention when wrong in comment with a doc fix.
- Did not exhaustively change these
- Wrestled doc example in RenderDiGraph#renderNode, not sure if I won
- Cleaned up InferWidths & CatchExceptions imports
- Added missing license message to a couple of files.
- fixed a couple of stale parameter names in scaladoc
- Added @unchecked to stop erasure warning in Emitting where emission annotations are collected
- Change types to [_] on match in RenameMap#recordAll to fix erasure warning
* Where possible change [[firrtl.ir.X]] to [[firrtl.ir.X X]] for better display in scaladoc
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/firrtl/RenameMap.scala')
| -rw-r--r-- | src/main/scala/firrtl/RenameMap.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/RenameMap.scala b/src/main/scala/firrtl/RenameMap.scala index 61f1d8f9..543fc1ad 100644 --- a/src/main/scala/firrtl/RenameMap.scala +++ b/src/main/scala/firrtl/RenameMap.scala @@ -97,9 +97,9 @@ final class RenameMap private (val underlying: mutable.HashMap[CompleteTarget, S */ def recordAll(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): Unit = map.foreach{ - case (from: IsComponent, tos: Seq[IsMember]) => completeRename(from, tos) - case (from: IsModule, tos: Seq[IsMember]) => completeRename(from, tos) - case (from: CircuitTarget, tos: Seq[CircuitTarget]) => completeRename(from, tos) + case (from: IsComponent, tos: Seq[_]) => completeRename(from, tos) + case (from: IsModule, tos: Seq[_]) => completeRename(from, tos) + case (from: CircuitTarget, tos: Seq[_]) => completeRename(from, tos) case other => Utils.throwInternalError(s"Illegal rename: ${other._1} -> ${other._2}") } |
