diff options
| author | Jack Koenig | 2019-08-13 12:09:27 +0530 |
|---|---|---|
| committer | GitHub | 2019-08-13 12:09:27 +0530 |
| commit | f08f8dbb3c480220f92923a7f3242fcbb644b65e (patch) | |
| tree | 45cdb7543f6252ad2feb5aaf4e0e0580d3d27565 /src/main/scala/firrtl/PrimOps.scala | |
| parent | 63e88b6e1696e2c8d6da91f6f5eb128a9d0395ae (diff) | |
Infer reset (#1068)
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1>
* Enhance async reset initial value literal check to support aggregates
Diffstat (limited to 'src/main/scala/firrtl/PrimOps.scala')
| -rw-r--r-- | src/main/scala/firrtl/PrimOps.scala | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala index 0f1ecff7..1a513352 100644 --- a/src/main/scala/firrtl/PrimOps.scala +++ b/src/main/scala/firrtl/PrimOps.scala @@ -203,43 +203,38 @@ object PrimOps extends LazyLogging { case _: UIntType => UIntType(w1) case _: SIntType => UIntType(w1) case _: FixedType => UIntType(w1) - case ClockType => UIntType(IntWidth(1)) + case ClockType | AsyncResetType | ResetType => UIntType(IntWidth(1)) case AnalogType(w) => UIntType(w1) - case AsyncResetType => UIntType(IntWidth(1)) case _ => UnknownType } case AsSInt => t1 match { case _: UIntType => SIntType(w1) case _: SIntType => SIntType(w1) case _: FixedType => SIntType(w1) - case ClockType => SIntType(IntWidth(1)) + case ClockType | AsyncResetType | ResetType => SIntType(IntWidth(1)) case _: AnalogType => SIntType(w1) - case AsyncResetType => SIntType(IntWidth(1)) case _ => UnknownType } case AsFixedPoint => t1 match { case _: UIntType => FixedType(w1, c1) case _: SIntType => FixedType(w1, c1) case _: FixedType => FixedType(w1, c1) - case ClockType => FixedType(IntWidth(1), c1) + case ClockType | AsyncResetType | ResetType => FixedType(IntWidth(1), c1) case _: AnalogType => FixedType(w1, c1) - case AsyncResetType => FixedType(IntWidth(1), c1) case _ => UnknownType } case AsClock => t1 match { case _: UIntType => ClockType case _: SIntType => ClockType - case ClockType => ClockType + case ClockType | AsyncResetType | ResetType => ClockType case _: AnalogType => ClockType - case AsyncResetType => ClockType case _ => UnknownType } case AsAsyncReset => t1 match { case _: UIntType => AsyncResetType case _: SIntType => AsyncResetType - case ClockType => AsyncResetType + case ClockType | AsyncResetType | ResetType => AsyncResetType case _: AnalogType => AsyncResetType - case AsyncResetType => AsyncResetType case _ => UnknownType } case Shl => t1 match { |