Merge pull request #1124 from freechipsproject/gender-to-flow

Gender to Flow

1 files changed, 5 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 274ccf74..05cdbe96 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -29,7 +29,7 @@ class IRToWorkingIR extends CoreTransform {
   def transforms = Seq(passes.ToWorkingIR)
 }
 
-/** Resolves types, kinds, and genders, and checks the circuit legality.
+/** Resolves types, kinds, and flows, and checks the circuit legality.
   * Operates on working IR nodes and high Firrtl.
   */
 class ResolveAndCheck extends CoreTransform {
@@ -43,8 +43,8 @@ class ResolveAndCheck extends CoreTransform {
     passes.Uniquify,
     passes.ResolveKinds,
     passes.InferTypes,
-    passes.ResolveGenders,
-    passes.CheckGenders,
+    passes.ResolveFlows,
+    passes.CheckFlows,
     new passes.InferWidths,
     passes.CheckWidths,
     new firrtl.transforms.InferResets)
@@ -70,7 +70,7 @@ class HighFirrtlToMiddleFirrtl extends CoreTransform {
     passes.InferTypes,
     passes.CheckTypes,
     new checks.CheckResets,
-    passes.ResolveGenders,
+    passes.ResolveFlows,
     new passes.InferWidths,
     passes.CheckWidths,
     passes.ConvertFixedToSInt,
@@ -89,7 +89,7 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform {
     passes.LowerTypes,
     passes.ResolveKinds,
     passes.InferTypes,
-    passes.ResolveGenders,
+    passes.ResolveFlows,
     new passes.InferWidths,
     passes.Legalize,
     new firrtl.transforms.RemoveReset,