diff options
| author | Jack | 2016-05-10 01:38:20 -0700 |
|---|---|---|
| committer | Jack Koenig | 2016-06-10 16:43:06 -0700 |
| commit | f162263c05643c0851c5200fff2fc356f97843cd (patch) | |
| tree | e5d49ea105d189320439aa2f1b0b9ab6ec98b603 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 58d9f1d50c07d999776c76259fadbdfd52c564fc (diff) | |
API Cleanup - AST
trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 3db83406..33cb70db 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -30,6 +30,7 @@ package firrtl import com.typesafe.scalalogging.LazyLogging import java.io.Writer import firrtl.passes.Pass +import firrtl.ir.Circuit // =========================================== // Utility Traits @@ -67,7 +68,7 @@ class Chisel3ToHighFirrtl () extends Transform with SimpleRun { run(circuit, passSeq) } -// Converts from the bare intermediate representation (IR.scala) +// Converts from the bare intermediate representation (ir.scala) // to a working representation (WIR.scala) class IRToWorkingIR () extends Transform with SimpleRun { val passSeq = Seq(passes.ToWorkingIR) |