diff options
| author | Adam Izraelevitz | 2016-08-02 12:24:13 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-02 12:24:13 -0700 |
| commit | dc7a1470e1a64643c387e328030059735d8d2c4c (patch) | |
| tree | 29b0699b2fa9e3e18de99b3b39fd1d41ba24775b /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 6505168958e44bde9ba6828c0f7c03a04528fdec (diff) | |
| parent | c951e7453303f7aaf0c281f88a76ae2ba017ed38 (diff) | |
Merge pull request #203 from ucb-bar/fix_mem_infer
Fix mem infer
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 95398356..7c239b10 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -188,6 +188,7 @@ class LowFirrtlCompiler extends Compiler { new passes.InlineInstances(TransID(0)), new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), + new passes.InferReadWrite(TransID(-1)), new MiddleFirrtlToLowFirrtl(), new EmitFirrtl(writer) ) @@ -200,6 +201,7 @@ class VerilogCompiler extends Compiler { new IRToWorkingIR(), new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), + new passes.InferReadWrite(TransID(-1)), new MiddleFirrtlToLowFirrtl(), new passes.InlineInstances(TransID(0)), new EmitVerilogFromLowFirrtl(writer) |