diff options
| author | Donggyu | 2016-09-25 15:27:23 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-25 15:27:23 -0700 |
| commit | 7c4fa71a062f0c18a3af13c9e8853fdec2818da9 (patch) | |
| tree | d08bd63808f505e09a35d68c7997722e62b64fea /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 744ea401553cabfb31c7cc32aecfd8ca2764d1b8 (diff) | |
| parent | 350b0d5249c33880f867f41d4e8a0d6ffb87423f (diff) | |
Merge pull request #260 from ucb-bar/mem_latency_pipes
Mem latency pipes
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index cd77fa3e..c7b7f5dd 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -145,6 +145,8 @@ class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with Simple passes.ConstProp, passes.Legalize, passes.VerilogWrap, + passes.VerilogMemDelays, + passes.ConstProp, passes.SplitExpressions, passes.CommonSubexpressionElimination, passes.DeadCodeElimination, |