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authorazidar2016-08-19 16:58:34 -0700
committerDonggyu Kim2016-09-07 10:58:08 -0700
commit6255d5e398ae21dbc75db907bb9a9b24bc09d2b3 (patch)
treecfff6e46fad44cc0c20eb079863b2a0d6d4aa993 /src/main/scala/firrtl/LoweringCompilers.scala
parent25b4a97b5fcc2b043f2c611f63c2497b8584cf55 (diff)
Added ReplaceSubAccesses before RemoveSubAccesses
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index f9a5864c..c8430d2b 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -104,6 +104,7 @@ class ResolveAndCheck () extends Transform with SimpleRun {
class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun {
val passSeq = Seq(
passes.PullMuxes,
+ passes.ReplaceAccesses,
passes.ExpandConnects,
passes.RemoveAccesses,
passes.ExpandWhens,