aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/LoweringCompilers.scala
diff options
context:
space:
mode:
authorJim Lawson2017-01-20 08:52:15 -0800
committerGitHub2017-01-20 08:52:15 -0800
commit58c1840c7db278417fcceaf035e9df7601233406 (patch)
tree29c6c3e1d1ad26f06f72b45cfe4f2ead7f83aee9 /src/main/scala/firrtl/LoweringCompilers.scala
parentefc367e883ffd8c0a239f04943e4bda5ce356da4 (diff)
parent51fde13c21825f87ee7fc854eb41215e02076bb5 (diff)
Merge branch 'master' into scaladocroot
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index c29ce01a..44d3a757 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -119,6 +119,12 @@ class HighFirrtlCompiler extends Compiler {
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, HighForm)
}
+/** Emits middle Firrtl input circuit */
+class MiddleFirrtlCompiler extends Compiler {
+ def emitter = new FirrtlEmitter
+ def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, MidForm)
+}
+
/** Emits lowered input circuit */
class LowFirrtlCompiler extends Compiler {
def emitter = new FirrtlEmitter