Merge pull request #198 from ucb-bar/add-chirrtl-check

Added a Chirrtl check for undeclared wires, etc.

1 files changed, 4 insertions, 2 deletions

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 9a2bc11f..036156dc 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -61,6 +61,7 @@ trait SimpleRun extends LazyLogging {
 // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL
 class Chisel3ToHighFirrtl () extends Transform with SimpleRun {
    val passSeq = Seq(
+      passes.CheckChirrtl,
       passes.CInferTypes,
       passes.CInferMDir,
       passes.RemoveCHIRRTL)
@@ -108,8 +109,9 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun {
       passes.CheckInitialization,
       passes.ResolveKinds,
       passes.InferTypes,
-      passes.ResolveGenders,
-      passes.InferWidths)
+      passes.ResolveGenders)
+      //passes.InferWidths,
+      //passes.CheckWidths)
    def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult =
       run(circuit, passSeq)
 }