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| author | Jack Koenig | 2016-09-07 11:24:08 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-07 11:24:08 -0700 |
| commit | 0c6db9ef0669e3fb92fcc0bda2085f934d065f0b (patch) | |
| tree | cfff6e46fad44cc0c20eb079863b2a0d6d4aa993 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 6a05468ed0ece1ace3019666b16f2ae83ef76ef9 (diff) | |
| parent | 6255d5e398ae21dbc75db907bb9a9b24bc09d2b3 (diff) | |
Merge pull request #256 from ucb-bar/fix_boom_errors
Fix performance bug with remove accesses
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index f9a5864c..c8430d2b 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -104,6 +104,7 @@ class ResolveAndCheck () extends Transform with SimpleRun { class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { val passSeq = Seq( passes.PullMuxes, + passes.ReplaceAccesses, passes.ExpandConnects, passes.RemoveAccesses, passes.ExpandWhens, |