diff options
| author | azidar | 2016-07-21 13:57:13 -0700 |
|---|---|---|
| committer | azidar | 2016-07-21 13:57:13 -0700 |
| commit | 0441a6df1eafd5db99c5cbcc0a07c5a6cb37f975 (patch) | |
| tree | 116ec7cbf7f94d70f5659abace4267f529b195f2 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | ab340febdc7a5418da945f9b79624d36e66e26db (diff) | |
Added a Chirrtl check for undeclared wires, etc.
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 9a2bc11f..29355e1a 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -61,6 +61,7 @@ trait SimpleRun extends LazyLogging { // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL class Chisel3ToHighFirrtl () extends Transform with SimpleRun { val passSeq = Seq( + passes.CheckChirrtl, passes.CInferTypes, passes.CInferMDir, passes.RemoveCHIRRTL) |