diff options
| author | Schuyler Eldridge | 2019-02-05 14:57:53 -0500 |
|---|---|---|
| committer | GitHub | 2019-02-05 14:57:53 -0500 |
| commit | d69c609fd41c2b6ca2993085bcd2923daa563bde (patch) | |
| tree | 3d7a3bacd8debc917cd5525d6fdecdee6a50e31c /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | fa0a6e2cbe2a78fc231f47b5b73d870669b54ade (diff) | |
| parent | 0a88492bfbbfe7e446b74776ec59cab69e73585b (diff) | |
Merge pull request #1004 from seldridge/issue-423
Add "mverilog" Compiler Option, MinimumVerilogEmitter
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index eab928c2..9969150d 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -119,6 +119,7 @@ class MinimumLowFirrtlOptimization extends CoreTransform { def inputForm = LowForm def outputForm = LowForm def transforms = Seq( + passes.RemoveValidIf, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.SplitExpressions) @@ -166,9 +167,9 @@ class VerilogCompiler extends Compiler { /** Emits Verilog without optimizations */ class MinimumVerilogCompiler extends Compiler { - def emitter = new VerilogEmitter + def emitter = new MinimumVerilogEmitter def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++ - Seq(new MinimumLowFirrtlOptimization, new BlackBoxSourceHelper) + Seq(new MinimumLowFirrtlOptimization) } /** Currently just an alias for the [[VerilogCompiler]] */ |