diff options
| author | Donggyu Kim | 2016-07-27 14:56:11 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-08-02 11:29:43 -0700 |
| commit | c951e7453303f7aaf0c281f88a76ae2ba017ed38 (patch) | |
| tree | 7374e2570f84d73ca826e6722941828ee6fc5be2 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 22350029c9a91c30abd849c17108f8bc24054a78 (diff) | |
make infer readwrite ports optional
turned on with '--inferRW <circuit name>'
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index c27ffce7..4d7ddfe0 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -107,7 +107,6 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { passes.ExpandConnects, passes.RemoveAccesses, passes.ExpandWhens, - passes.InferReadWrite, passes.CheckInitialization, passes.ConstProp, passes.ResolveKinds, @@ -190,6 +189,7 @@ class LowFirrtlCompiler extends Compiler { new passes.InlineInstances(TransID(0)), new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), + new passes.InferReadWrite(TransID(-1)), new MiddleFirrtlToLowFirrtl(), new EmitFirrtl(writer) ) @@ -202,6 +202,7 @@ class VerilogCompiler extends Compiler { new IRToWorkingIR(), new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), + new passes.InferReadWrite(TransID(-1)), new MiddleFirrtlToLowFirrtl(), new passes.InlineInstances(TransID(0)), new EmitVerilogFromLowFirrtl(writer) |