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| author | Jack | 2016-05-18 12:02:52 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-12 21:30:38 -0700 |
| commit | 9edf656e11084958d9e90807a4740a57b83babfe (patch) | |
| tree | 6bddf2376fe3e64668b5e59f350cfbbcf86dfaee /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | f7dd234f7c5a2dc03c42640db11b1d6509108643 (diff) | |
Legalize bit select. Run Legalize after PadWidths.
Bit selecting a literal resulted in invalid Verilog. Legalize now deals with
this by replacing any bits select of UInt or SInt literals with a new literal
composed of the selected bits. Legalize also is now run after PadWidths because
that pass introduces this issue.
Fixes #170
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index c8430d2b..4d40d9a8 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -124,7 +124,6 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun { val passSeq = Seq( - passes.Legalize, passes.LowerTypes, passes.ResolveKinds, passes.InferTypes, @@ -146,6 +145,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl passes.ConstProp, passes.PadWidths, passes.ConstProp, + passes.Legalize, passes.VerilogWrap, passes.SplitExpressions, passes.CommonSubexpressionElimination, |