diff options
| author | Jack Koenig | 2017-06-29 14:20:09 -0700 |
|---|---|---|
| committer | GitHub | 2017-06-29 14:20:09 -0700 |
| commit | 905cac96053caf4b6c87ac0b9c8addf313d1085c (patch) | |
| tree | 7d0bcf384f63e0176acdd70f9524369bb5bb4ce0 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 8eb69dd91e58915f8dad5e42da0a3fe686c628d8 (diff) | |
| parent | a0aeafa3d591f9bcc14eca6d8a41eb2155f1b5b0 (diff) | |
Merge pull request #617 from freechipsproject/const-prop-regs
Improvements to Constant Propagation and Testing
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 66ae1673..8dd9b180 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -98,12 +98,12 @@ class LowFirrtlOptimization extends CoreTransform { def outputForm = LowForm def transforms = Seq( passes.RemoveValidIf, - passes.ConstProp, + new firrtl.transforms.ConstantPropagation, passes.PadWidths, - passes.ConstProp, + new firrtl.transforms.ConstantPropagation, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter - passes.ConstProp, + new firrtl.transforms.ConstantPropagation, passes.SplitExpressions, passes.CommonSubexpressionElimination, new firrtl.transforms.DeadCodeElimination) |