diff options
| author | azidar | 2016-02-04 09:23:19 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:06 -0800 |
| commit | b32acb9a52a426087226284f4a1e2890cbdadc00 (patch) | |
| tree | e1771c82f9e707d95b507e67455a1e7fbbffea6a /src/main/scala/firrtl/IR.scala | |
| parent | ddeac42c426dbda9000eef1b74f8d5032c55f58f (diff) | |
Added Expand Whens pass
Diffstat (limited to 'src/main/scala/firrtl/IR.scala')
| -rw-r--r-- | src/main/scala/firrtl/IR.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala index 3656ef22..85870ab9 100644 --- a/src/main/scala/firrtl/IR.scala +++ b/src/main/scala/firrtl/IR.scala @@ -61,7 +61,7 @@ case class Mux(cond: Expression, tval: Expression, fval: Expression, tpe: Type) case class ValidIf(cond: Expression, value: Expression, tpe: Type) extends Expression case class UIntValue(value: BigInt, width: Width) extends Expression case class SIntValue(value: BigInt, width: Width) extends Expression -case class DoPrim(op: PrimOp, args: Seq[Expression], consts: Seq[BigInt], tpe: Type) extends Expression +case class DoPrim(op: PrimOp, args: Seq[Expression], consts: Seq[BigInt], tpe: Type) extends Expression trait Stmt extends AST case class DefWire(info: Info, name: String, tpe: Type) extends Stmt @@ -114,4 +114,3 @@ case class ExModule(info: Info, name: String, ports: Seq[Port]) extends Module case class Circuit(info: Info, modules: Seq[Module], main: String) extends AST - |