diff options
| author | Colin Schmidt | 2016-10-30 14:18:48 -0700 |
|---|---|---|
| committer | Donggyu | 2016-10-30 14:18:48 -0700 |
| commit | be87c1e2481d14a2e0b68668fbfd901d3416dddd (patch) | |
| tree | c1febd7d69a3079e5459de4d62ed3f1e7f80c470 /src/main/scala/firrtl/ExecutionOptionsManager.scala | |
| parent | 5b35f2d2722f72c81d2d6c507cd379be2a1476d8 (diff) | |
Keep package name + directory structure consistent (#354)
* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
Diffstat (limited to 'src/main/scala/firrtl/ExecutionOptionsManager.scala')
| -rw-r--r-- | src/main/scala/firrtl/ExecutionOptionsManager.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala index ff725e30..e4954610 100644 --- a/src/main/scala/firrtl/ExecutionOptionsManager.scala +++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala @@ -4,7 +4,7 @@ package firrtl import firrtl.Annotations._ import firrtl.Parser._ -import firrtl.passes.memlib.ReplSeqMemAnnotation +import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation} import logger.LogLevel import scopt.OptionParser @@ -267,7 +267,7 @@ trait HasFirrtlOptions { .valueName ("<circuit>") .foreach { x => firrtlOptions = firrtlOptions.copy( - annotations = firrtlOptions.annotations :+ passes.InferReadWriteAnnotation(x, TransID(-1)) + annotations = firrtlOptions.annotations :+ InferReadWriteAnnotation(x, TransID(-1)) ) }.text { "Enable readwrite port inference for the target circuit" |
