Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)

* Add --nodedup option to facilitate FIRRTL to verilog regression testing.

* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.

1 files changed, 10 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index 47083cb4..189701dc 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -7,6 +7,7 @@ import firrtl.Parser._
 import firrtl.ir.Circuit
 import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation}
 import firrtl.passes.clocklist.ClockListAnnotation
+import firrtl.transforms.NoCircuitDedupAnnotation
 import logger.LogLevel
 import scopt.OptionParser
 
@@ -476,6 +477,15 @@ trait HasFirrtlOptions {
       "Do NOT run dead code elimination"
     }
 
+  parser.opt[Unit]("no-dedup")
+    .foreach { _ =>
+      firrtlOptions = firrtlOptions.copy(
+        annotations = firrtlOptions.annotations :+ NoCircuitDedupAnnotation
+      )
+    }.text {
+    "Do NOT dedup modules"
+  }
+
   parser.note("")
 }