diff options
| author | Schuyler Eldridge | 2018-08-29 14:18:19 -0400 |
|---|---|---|
| committer | GitHub | 2018-08-29 14:18:19 -0400 |
| commit | a564d73f35703f8ba35b3e2c3263f1d9a65746fa (patch) | |
| tree | 81b63df0db1c3f9576c2d041b0c1884cc7be30ca /src/main/scala/firrtl/ExecutionOptionsManager.scala | |
| parent | 22cd17e0037b2f8ce15dcb5ef5e4792db3455fa1 (diff) | |
| parent | b6c89b2bb93dcc33900b1eb4351f68e82a75671e (diff) | |
Merge pull request #878 from seldridge/issue-764-refactor-pr-pointer-systemVerilogCompiler
[F764.3] Add explicit SystemVerilogCompiler class
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/ExecutionOptionsManager.scala')
| -rw-r--r-- | src/main/scala/firrtl/ExecutionOptionsManager.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala index bb5e68a3..1754338c 100644 --- a/src/main/scala/firrtl/ExecutionOptionsManager.scala +++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala @@ -209,7 +209,7 @@ extends ComposableOptions { case "low" => new LowFirrtlCompiler() case "middle" => new MiddleFirrtlCompiler() case "verilog" => new VerilogCompiler() - case "sverilog" => new VerilogCompiler() + case "sverilog" => new SystemVerilogCompiler() } } |