diff options
| author | Jim Lawson | 2017-05-11 16:55:08 -0700 |
|---|---|---|
| committer | GitHub | 2017-05-11 16:55:08 -0700 |
| commit | fba12e01fda28a72b3c00116b52f8aee8bce0677 (patch) | |
| tree | b532b48020d11c41815779c9f8b2e0092cdaa798 /src/main/scala/firrtl/Emitter.scala | |
| parent | 41c28e5292180b455d677e63d6cafbc649063b41 (diff) | |
Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 933d98c5..696856a6 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -187,7 +187,7 @@ class VerilogEmitter extends SeqTransform with Emitter { } def wref(n: String, t: Type) = WRef(n, t, ExpKind, UNKNOWNGENDER) def remove_root(ex: Expression): Expression = ex match { - case ex: WSubField => ex.exp match { + case ex: WSubField => ex.expr match { case (e: WSubField) => remove_root(e) case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind, UNKNOWNGENDER) } @@ -223,7 +223,7 @@ class VerilogEmitter extends SeqTransform with Emitter { case (e: ValidIf) => emit(Seq(cast(e.value)),top + 1) case (e: WRef) => w write e.serialize case (e: WSubField) => w write LowerTypes.loweredName(e) - case (e: WSubAccess) => w write s"${LowerTypes.loweredName(e.exp)}[${LowerTypes.loweredName(e.index)}]" + case (e: WSubAccess) => w write s"${LowerTypes.loweredName(e.expr)}[${LowerTypes.loweredName(e.index)}]" case (e: WSubIndex) => w write e.serialize case (e: Literal) => v_print(e) case (e: VRandom) => w write s"{${e.nWords}{$$random}}" |