Infer reset (#1068)

* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1>
* Enhance async reset initial value literal check to support aggregates

1 files changed, 6 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 8e6408fe..854e1876 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -231,7 +231,12 @@ class VerilogEmitter extends SeqTransform with Emitter {
     x match {
       case (e: DoPrim) => emit(op_stream(e), top + 1)
       case (e: Mux) => {
-        if(e.tpe == ClockType) throw EmitterException("Cannot emit clock muxes directly")
+        if (e.tpe == ClockType) {
+          throw EmitterException("Cannot emit clock muxes directly")
+        }
+        if (e.tpe == AsyncResetType) {
+          throw EmitterException("Cannot emit async reset muxes directly")
+        }
         emit(Seq(e.cond," ? ",cast(e.tval)," : ",cast(e.fval)),top + 1)
       }
       case (e: ValidIf) => emit(Seq(cast(e.value)),top + 1)