Replacematcherror - catch exceptions and convert to internal error. (#424)

* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.

* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.

* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.

1 files changed, 9 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 84b34339..5753fc17 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -120,7 +120,7 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
         case WDefInstance(_, _, name, _) =>
           modules += map(name)
           stmt
-        case _: WDefInstanceConnector => throwInternalError
+        case _: WDefInstanceConnector => throwInternalError(Some(s"unrecognized statement: $stmt"))
         case other => other map onStmt
       }
       onStmt(mod.body)
@@ -191,7 +191,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       case (e: WSubField) => remove_root(e)
       case (_: WRef) => WRef(ex.name, ex.tpe, InstanceKind, UNKNOWNGENDER)
     }
-    case _ => error("Shouldn't be here")
+    case _ => throwInternalError(Some(s"shouldn't be here: remove_root($ex)"))
   }
   /** Turn Params into Verilog Strings */
   def stringify(param: Param): String = param match {
@@ -205,7 +205,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       val wx = bitWidth(tpe) - 1
       if (wx > 0) s"[$wx:0]" else ""
     case ClockType => ""
-    case _ => error("Trying to write unsupported type in the Verilog Emitter")
+    case _ => throwInternalError(Some(s"trying to write unsupported type in the Verilog Emitter: $tpe"))
   }
   def emit(x: Any)(implicit w: Writer) { emit(x, 0) }
   def emit(x: Any, top: Int)(implicit w: Writer) {
@@ -214,6 +214,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       case (t: SIntType) => Seq("$signed(",e,")")
       case ClockType => e
       case AnalogType(_) => e
+      case _ => throwInternalError(Some(s"unrecognized cast: $e"))
     }
     x match {
       case (e: DoPrim) => emit(op_stream(e), top + 1)
@@ -240,7 +241,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       case (s: Seq[Any]) =>
         s foreach (emit(_, top + 1))
         if (top == 0) w write "\n"
-      case x => println(x); throwInternalError;
+      case x => throwInternalError(Some(s"trying to emit unsupported operator: $x"))
     }
   }
 
@@ -254,6 +255,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
          case '-' => s"-$width'sh${stringLiteral.tail}"
          case _ => s"$width'sh${stringLiteral}"
        })
+     case _ => throwInternalError(Some(s"attempt to print unrecognized expression: $e"))
    }
 
    def op_stream(doprim: DoPrim): Seq[Any] = {
@@ -266,16 +268,19 @@ class VerilogEmitter extends SeqTransform with Emitter {
          case Some(_) => e.tpe match {
            case (_: SIntType) => Seq("$signed(", e, ")")
            case (_: UIntType) => Seq("$signed({1'b0,", e, "})")
+           case _ => throwInternalError(Some(s"unrecognized type: $e"))
          }
        }
      }
      def cast(e: Expression): Any = doprim.tpe match {
        case (t: UIntType) => e
        case (t: SIntType) => Seq("$signed(",e,")")
+       case _ => throwInternalError(Some(s"cast - unrecognized type: $e"))
      }
      def cast_as(e: Expression): Any = e.tpe match {
        case (t: UIntType) => e
        case (t: SIntType) => Seq("$signed(",e,")")
+       case _ => throwInternalError(Some(s"cast_as - unrecognized type: $e"))
      }
      def a0: Expression = doprim.args.head
      def a1: Expression = doprim.args(1)