diff options
| author | grebe | 2017-01-19 09:12:13 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-01-19 09:12:13 -0800 |
| commit | b0623fe1856caeba11cda1ccaf68f094489169a7 (patch) | |
| tree | 38b1c247c9a3a51ca0a824eac1248933df2a2a69 /src/main/scala/firrtl/Emitter.scala | |
| parent | 8a1cdf15d131e086ddc9de6bfe8cd90ed7fb3eb7 (diff) | |
Verilog rem fix (#404)
* Add pass that fixes up widths with modulus operator for verilog
* Add basic test for Verilog emission of Rem
* Oops, left in some printlns.
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index e40a18a4..a290ced4 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -562,6 +562,7 @@ class VerilogEmitter extends Emitter with PassBased { } def passSeq = Seq( + passes.VerilogModulusCleanup, passes.VerilogWrap, passes.VerilogRename, passes.VerilogPrep) |