diff options
| author | Donggyu Kim | 2016-09-07 21:03:07 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-13 13:34:15 -0700 |
| commit | 590c3f2cd959c3c125c6511287294aec8409b57b (patch) | |
| tree | 1ec4b2b434e01ea86a7db19af830b82b7ac61d78 /src/main/scala/firrtl/Emitter.scala | |
| parent | a38930a841cf4f328c81bd65844eee5e0fa24b54 (diff) | |
remove Utils.get_type
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 8b1360ab..e8423dfe 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -260,7 +260,7 @@ class VerilogEmitter extends Emitter { simlist += s s case (s: DefNode) => - val e = WRef(s.name, get_type(s), NodeKind(), MALE) + val e = WRef(s.name, s.value.tpe, NodeKind(), MALE) netlist(e) = s.value s case (s) => s |