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authorSchuyler Eldridge2019-01-25 14:04:16 -0500
committerSchuyler Eldridge2019-02-05 14:09:42 -0500
commit334c9bbe5061a3bcb72df971ec555de7df0ba36c (patch)
treeac57432a334a14b777ca773a95d260b3d6660c81 /src/main/scala/firrtl/Emitter.scala
parentfa0a6e2cbe2a78fc231f47b5b73d870669b54ade (diff)
Add "mverilog" Compiler Option, Compiler Fixes
This adds "mverilog" to the "--compiler" command line option. This will run the MinimumVerilogCompiler. This additionally fixes the MinimumVerilogCompiler such that DeadCodeElimination will not be run (it's not supposed to be). This is done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog, that strips the DeadCodeElimination step from its parent. Additionally, BlackBoxSourceHelper is removed from the MinimumVerilogCompiler since this will be run by the VerilogEmitter already. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
-rw-r--r--src/main/scala/firrtl/Emitter.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 67bd1583..8049e33c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -882,3 +882,13 @@ class VerilogEmitter extends SeqTransform with Emitter {
state.copy(annotations = newAnnos ++ state.annotations)
}
}
+
+class MinimumVerilogEmitter extends VerilogEmitter with Emitter {
+
+
+ override def transforms = super.transforms.filter{
+ case _: DeadCodeElimination => false
+ case _ => true
+ }
+
+}