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authorAdam Izraelevitz2018-11-27 13:28:12 -0800
committerGitHub2018-11-27 13:28:12 -0800
commit17d1d2db772f90b039210874aadb11a8a807baba (patch)
treef303cee0e5eeafffa73f93ee16a91be7aca1d34b /src/main/scala/firrtl/Emitter.scala
parent82f62e04ed71d4507b72f784b3c230dda1262340 (diff)
Add foreach as alternative to map (#952)
* Added Foreachers * Changed CheckTypes to use foreach * Check widths now uses foreach * Finished merge, added foreachers to added stmts * Address reviewer feedback
Diffstat (limited to 'src/main/scala/firrtl/Emitter.scala')
-rw-r--r--src/main/scala/firrtl/Emitter.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 578782ce..7be049ed 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -125,6 +125,9 @@ case class VRandom(width: BigInt) extends Expression {
def mapExpr(f: Expression => Expression): Expression = this
def mapType(f: Type => Type): Expression = this
def mapWidth(f: Width => Width): Expression = this
+ def foreachExpr(f: Expression => Unit): Unit = Unit
+ def foreachType(f: Type => Unit): Unit = Unit
+ def foreachWidth(f: Width => Unit): Unit = Unit
}
class VerilogEmitter extends SeqTransform with Emitter {