API Cleanup - Statement

trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline

1 files changed, 30 insertions, 36 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 7af2017c..c8657131 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -275,15 +275,15 @@ class VerilogEmitter extends Emitter {
    def emit_verilog (m:Module) : DefModule = {
       mname = m.name
       val netlist = LinkedHashMap[WrappedExpression,Expression]()
-      val simlist = ArrayBuffer[Stmt]()
+      val simlist = ArrayBuffer[Statement]()
       val namespace = Namespace(m)
-      def build_netlist (s:Stmt) : Stmt = {
+      def build_netlist (s:Statement) : Statement = {
          s match {
-            case (s:Connect) => netlist(s.loc) = s.exp
+            case (s:Connect) => netlist(s.loc) = s.expr
             case (s:IsInvalid) => {
                val n = namespace.newTemp
-               val e = wref(n,tpe(s.exp))
-               netlist(s.exp) = e
+               val e = wref(n,tpe(s.expr))
+               netlist(s.expr) = e
             }
             case (s:Conditionally) => simlist += s
             case (s:DefNode) => {
@@ -379,10 +379,10 @@ class VerilogEmitter extends Emitter {
       }
       def initialize (e:Expression) = initials += Seq(e," = ",rand_string(tpe(e)),";")
       def initialize_mem(s: DefMemory) = {
-        val index = WRef("initvar", s.data_type, ExpKind(), UNKNOWNGENDER)
-        val rstring = rand_string(s.data_type)
+        val index = WRef("initvar", s.dataType, ExpKind(), UNKNOWNGENDER)
+        val rstring = rand_string(s.dataType)
         initials += Seq("for (initvar = 0; initvar < ", s.depth, "; initvar = initvar+1)")
-        initials += Seq(tab, WSubAccess(wref(s.name, s.data_type), index, s.data_type, FEMALE), " = ", rstring,";")
+        initials += Seq(tab, WSubAccess(wref(s.name, s.dataType), index, s.dataType, FEMALE), " = ", rstring,";")
       }
       def instantiate (n:String,m:String,es:Seq[Expression]) = {
          instdeclares += Seq(m," ",n," (")
@@ -447,9 +447,9 @@ class VerilogEmitter extends Emitter {
             }
          }}
       }
-      def build_streams (s:Stmt) : Stmt = {
+      def build_streams (s:Statement) : Statement = {
          s match {
-            case (s:Empty) => s
+            case EmptyStmt => s
             case (s:Connect) => s
             case (s:DefWire) => 
                declare("wire",s.name,s.tpe)
@@ -462,16 +462,10 @@ class VerilogEmitter extends Emitter {
                initialize(e)
             }
             case (s:IsInvalid) => {
-               val wref = netlist(s.exp).as[WRef].get
-               declare("reg",wref.name,tpe(s.exp))
+               val wref = netlist(s.expr).as[WRef].get
+               declare("reg",wref.name,tpe(s.expr))
                initialize(wref)
             }
-            case (s:DefPoison) => {
-               val n = s.name
-               val e = wref(n,s.tpe)
-               declare("reg",n,tpe(e))
-               initialize(e)
-            }
             case (s:DefNode) => {
                declare("wire",s.name,tpe(s.value))
                assign(WRef(s.name,tpe(s.value),NodeKind(),MALE),s.value)
@@ -491,7 +485,7 @@ class VerilogEmitter extends Emitter {
                   WSubField(x,f,t2,UNKNOWNGENDER)
                }
       
-               declare("reg",s.name,VectorType(s.data_type,s.depth))
+               declare("reg",s.name,VectorType(s.dataType,s.depth))
                initialize_mem(s)
                for (r <- s.readers ) {
                   val data = mem_exp(r,"data")
@@ -507,10 +501,10 @@ class VerilogEmitter extends Emitter {
                   //; Read port
                   assign(addr,netlist(addr)) //;Connects value to m.r.addr
                   assign(en,netlist(en))     //;Connects value to m.r.en
-                  val addrx = delay(addr,s.read_latency,clk)
-                  val enx = delay(en,s.read_latency,clk)
-                  val mem_port = WSubAccess(mem,addrx,s.data_type,UNKNOWNGENDER)
-                  val depthValue = UIntValue(s.depth, IntWidth(BigInt(s.depth).bitLength))
+                  val addrx = delay(addr,s.readLatency,clk)
+                  val enx = delay(en,s.readLatency,clk)
+                  val mem_port = WSubAccess(mem,addrx,s.dataType,UNKNOWNGENDER)
+                  val depthValue = UIntLiteral(s.depth, IntWidth(BigInt(s.depth).bitLength))
                   val garbageGuard = DoPrim(GREATER_EQ_OP, Seq(addrx, depthValue), Seq(), UnknownType)
                   val garbageMux = Mux(garbageGuard, VRandom, mem_port, UnknownType)
                   synSimAssign(data, mem_port, garbageMux)
@@ -535,11 +529,11 @@ class VerilogEmitter extends Emitter {
                   assign(mask,netlist(mask))
                   assign(en,netlist(en))
    
-                  val datax = delay(data,s.write_latency - 1,clk)
-                  val addrx = delay(addr,s.write_latency - 1,clk)
-                  val maskx = delay(mask,s.write_latency - 1,clk)
-                  val enx = delay(en,s.write_latency - 1,clk)
-                  val mem_port = WSubAccess(mem,addrx,s.data_type,UNKNOWNGENDER)
+                  val datax = delay(data,s.writeLatency - 1,clk)
+                  val addrx = delay(addr,s.writeLatency - 1,clk)
+                  val maskx = delay(mask,s.writeLatency - 1,clk)
+                  val enx = delay(en,s.writeLatency - 1,clk)
+                  val mem_port = WSubAccess(mem,addrx,s.dataType,UNKNOWNGENDER)
                   update(mem_port,datax,clk,AND(enx,maskx))
                }
    
@@ -569,18 +563,18 @@ class VerilogEmitter extends Emitter {
                   assign(wmode,netlist(wmode))
    
                   //; Delay new signals by latency
-                  val raddrx = delay(addr,s.read_latency,clk)
-                  val waddrx = delay(addr,s.write_latency - 1,clk)
-                  val enx = delay(en,s.write_latency - 1,clk)
-                  val rmodx = delay(wmode,s.write_latency - 1,clk)
-                  val datax = delay(data,s.write_latency - 1,clk)
-                  val maskx = delay(mask,s.write_latency - 1,clk)
+                  val raddrx = delay(addr,s.readLatency,clk)
+                  val waddrx = delay(addr,s.writeLatency - 1,clk)
+                  val enx = delay(en,s.writeLatency - 1,clk)
+                  val rmodx = delay(wmode,s.writeLatency - 1,clk)
+                  val datax = delay(data,s.writeLatency - 1,clk)
+                  val maskx = delay(mask,s.writeLatency - 1,clk)
    
                   //; Write 
    
-                  val rmem_port = WSubAccess(mem,raddrx,s.data_type,UNKNOWNGENDER)
+                  val rmem_port = WSubAccess(mem,raddrx,s.dataType,UNKNOWNGENDER)
                   assign(rdata,rmem_port)
-                  val wmem_port = WSubAccess(mem,waddrx,s.data_type,UNKNOWNGENDER)
+                  val wmem_port = WSubAccess(mem,waddrx,s.dataType,UNKNOWNGENDER)
 
                   val tempName = namespace.newTemp
                   val tempExp = AND(enx,maskx)