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authorAndrew Waterman2016-04-21 14:29:44 -0700
committerjackkoenig2016-04-21 15:54:02 -0700
commitec32c852b57a42c7741f8ae27d59c21fcdb86a82 (patch)
tree1ade1c970813a59007313f9d8a109311d3e683d9 /src/main/scala/firrtl/Compiler.scala
parentd2268e388c16481b3716619f2f27e88909f37914 (diff)
Avoid Lint errors connecting wide signals to narrow ones
Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
-rw-r--r--src/main/scala/firrtl/Compiler.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 69450a67..fda4b7e3 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -73,11 +73,11 @@ object VerilogCompiler extends Compiler {
RemoveAccesses,
ExpandWhens,
CheckInitialization,
- Legalize,
ResolveKinds,
InferTypes,
ResolveGenders,
InferWidths,
+ Legalize,
LowerTypes,
ResolveKinds,
InferTypes,