diff options
| author | azidar | 2016-02-08 22:47:43 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:07 -0800 |
| commit | a9afec2145fe27a26c51fca7e169495114c5108d (patch) | |
| tree | 39b232e7bd67cec9c8a65807d92c51b5a44ad764 /src/main/scala/firrtl/Compiler.scala | |
| parent | 32f26d3939980644ddd573c1fcf1dd985a150947 (diff) | |
Added chirrtl passes, need to update parser
Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 2998232f..78ea644d 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -23,6 +23,9 @@ object VerilogCompiler extends Compiler { val passes = Seq( //CheckHighForm, //FromCHIRRTL, + CInferTypes, + CInferMDir, + RemoveCHIRRTL, ToWorkingIR, ResolveKinds, InferTypes, |