diff options
| author | azidar | 2016-02-06 09:59:13 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:07 -0800 |
| commit | 69597a7d57236bc43c964f7714bfa8ed53bf3bee (patch) | |
| tree | dd9d9870fe4fb2d21690d1757177fd10facfab99 /src/main/scala/firrtl/Compiler.scala | |
| parent | bf900917c50a440632dbcaae17bcfe9613d14452 (diff) | |
Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of rocketchip
Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 34feab99..d2f9fc0e 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -22,6 +22,7 @@ object VerilogCompiler extends Compiler { // Copied from Stanza implementation val passes = Seq( //CheckHighForm, + FromCHIRRTL, ToWorkingIR, ResolveKinds, InferTypes, @@ -31,14 +32,20 @@ object VerilogCompiler extends Compiler { ExpandConnects, RemoveAccesses, ExpandWhens, - CheckInitialization, + //CheckInitialization, ConstProp, - ToWorkingIR, ResolveKinds, InferTypes, ResolveGenders, InferWidths, - LowerTypes + LowerTypes, + ResolveKinds, + InferTypes, + ResolveGenders, + InferWidths, + VerilogWrap, + SplitExp, + VerilogRename ) def run(c: Circuit, w: Writer) { |