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authorjackkoenig2016-04-13 17:39:59 -0700
committerjackkoenig2016-04-22 13:46:16 -0700
commit55375ad6e561fcb78349c9344d2e2c5d942d5edc (patch)
tree1084a8a44f88c68fdaa99a591613c294b938e58f /src/main/scala/firrtl/Compiler.scala
parent6ddd8303725d8897f69d8fb971f1df6c585d3656 (diff)
Add Uniquify Pass
Also add pass to Verilog Compiler list of passes This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.
Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
-rw-r--r--src/main/scala/firrtl/Compiler.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index fda4b7e3..cf2fc43d 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -64,6 +64,9 @@ object VerilogCompiler extends Compiler {
ResolveKinds,
InferTypes,
CheckTypes,
+ Uniquify,
+ ResolveKinds,
+ InferTypes,
ResolveGenders,
CheckGenders,
InferWidths,